1. Field of the Invention
The present invention relates to a circuit design technology, and specifically relates to a circuit design technology for facilitating timing adjustment for a circuit whose layout has been designed.
2. Description of the Related Art
As a scale increase, a speed increase, and miniaturization of a semiconductor chip advance, LSI (Large Scale Integration) design is getting complicated. In addition, recently, importance of adapting to DFT (Design For Test), adapting to increasing complexity of clock circuit due to insertion of a gated clock cell for decreasing power consumption, and fine-tuning timing in an interface (I/F) with an external DRAM circuit is increasing. As a result, a method for adjusting timing highly precisely in a short TAT (Turn Around Time) is being sought.
Since adjusting (correcting) the timing during LSI development requires a large amount of processing time since a layout process is conducted again after the timing is adjusted. Also, since the layout process is repeated, cell placement and routing change slightly, and consequently, a problem such as a new timing error occurs.